// Copyright (C) 1953-2022 NUDT
// Verilog module name - command_encapsulate_inex 
// Version: V3.4.0.20220228
// Created:
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module command_encapsulate_inex
(
       i_clk,
       i_rst_n,
       
       iv_hcp_int_command  ,  
	   i_hcp_int_command_wr,   
       iv_hcp_ext_command  ,   
       i_hcp_ext_command_wr, 

       ov_command_ack,
       o_command_ack_wr
);
// I/O
// i_clk & rst
input                  i_clk;
input                  i_rst_n; 
//nmac data
input      [65:0]      iv_hcp_int_command  ;            
input                  i_hcp_int_command_wr;           
input      [65:0]      iv_hcp_ext_command  ;            
input                  i_hcp_ext_command_wr;  

output reg [65:0]	   ov_command_ack;
output reg	           o_command_ack_wr;
//////////////////////////////////////////////////
//                  state                       //
//////////////////////////////////////////////////
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
        ov_command_ack         <= 66'b0;
        o_command_ack_wr       <= 1'b0;     
    end
    else begin     
        if(i_hcp_ext_command_wr)begin
            ov_command_ack          <= iv_hcp_ext_command;//{iv_hcp_ext_command[63:62],2'b01,iv_hcp_ext_command[61:0]};
            o_command_ack_wr        <= 1'b1;  
        end      
        else if(i_hcp_int_command_wr)begin
            ov_command_ack          <= iv_hcp_int_command;//{iv_hcp_int_command[63:62],2'b00,iv_hcp_int_command[61:0]};
            o_command_ack_wr        <= 1'b1;  
        end        
        else begin
            ov_command_ack         <= 66'b0;
            o_command_ack_wr       <= 1'b0;         
        end
    end
end    
endmodule
    